Integrated circuit (IC) chips are formed on semiconductor wafers at increasingly smaller scale. In current technology nodes, such as 7, 10 and 14 nanometer technologies, transistor devices are constructed as three-dimensional (3D) fin field effect transistor (FINFET) structures. However, chipmakers face a myriad of challenges at 5 nm, 3 nm and beyond. Currently, traditional chip scaling continues to slow as process complexities and costs escalate at each node.
A potential solution to this chip scaling problem is gate-all-around technology. One example of a complex gate-all-around technology is a complementary FET (CFET) where nFET and pFET nanowires/nanosheets are vertically stacked on top of each other. However, one of the processing complexities of CFETs that needs to be addressed at nodes beyond 7 nm is independently growing the nFET and pFET source/drain Epitaxy while maintaining vertical integration and electrical disconnection. Using a conventional nanowire/nanosheet source/drain Epitaxy process for CFETs would form superposed n-doped Epitaxy and p-doped Epitaxy, making it challenging to form independent n- and p-contacts and especially difficult for wrap-around contacts. Thus, a method of forming CFETs with wrap around contacts that maintain vertical integration and electrical disconnection of the nFET and pFET source/drain Epitaxy is needed.
Furthermore, optimizing source/drain contact resistance remains a critical aspect to successful technology scaling. In the instance of complementary metal-oxide-semiconductor (CMOS) technology, access resistance is limited by contact resistance which is strongly dependent on the contact area. Therefore, a contact that wraps around the source/drain Epitaxy is desirable since it provides a way to increase the effective contact area while preserving aggressively scaled contacted poly pitch (CPP; also known as transistor gate pitch).